Soldering of a semiconductor chip to a substrate
US6206269A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of soldering a semiconductor chip to a substrate, such as to a capsule in an RF-power transistor, for instance. The semiconductor chip is provided with an adhesion layer consisting of a first material composition. A solderable layer consisting of a second material composition is disposed on this adhesion layer. An antioxidation layer consisting of a third material composition is disposed on said solderable layer. The antioxidation layer is coated with a layer of gold-tin solder. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and chip are exposed to an inert environment to which a reducing gas is delivered and the capsule and chip are subjected to a pressure substantially beneath atmospheric pressure whilst the gold-tin solder is heated to a temperature above its melting point. The gas pressure is increased whilst the gold-tin solder is molten and the temperature is lowered when a predetermined gas pressure is exceeded, so that the gold-tin solder will solidify.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.