Resist developing process
US6207352A · kind A · utility
2Cited by
2References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 31, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jul 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/3021
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A developing process for obtaining a resist pattern on a semiconductor wafer includes puddling a developer on a wafer and holding a wafer inclined at a predetermined tilt angle in the puddled condition and repeating alternately stoppage and slow rotation plural times. This can make the central pattern width narrower selectively simply by apparatus adjustment, in case where, otherwise the pattern width of a wafer's central portion becomes wide, thereby achieving an increased pattern uniformity of the wafer and serve as improving the performances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.