Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and IC card
US6207473A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Mar 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method includes the steps of integrally fabricating a plurality of circuit elements (41) on a substrate (1a), forming electrode bumps (11) on electrode pads (11b) conducting with circuit elements (41), forming a scribe line or a scribe line mark (21a) at a prescribed position of substrate (1a), and sticking an anisotropically conductive film (30) to cover each of the electrode bumps (11) and the scribe line or the scribe line mark (21a). The step of forming the electrode bumps (11) and the step of forming the scribe line or the scribe line mark (21a) are performed simultaneously. The electrode bumps (11) and the scribe line or the scribe line mark (21a) are preferably formed of gold. By the manufacturing method, even when an anisotropically conductive film is stuck on a semiconductor wafer having a plurality of circuit elements formed, the circuit elements can be diced as desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.