Method of manufacturing integrated circuit devices
US6207570A · kind A · utility
24Cited by
10References
35Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Aug 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing integrated circuit apparatuses; particularly, 1) a method for removing barrier material that lies between copper conductors in damascene interconnections, and 2) a method for removing a thin layer of silicon nitride material that has been intentionally un-etched during the formation of trenches and vias in damascene interconnect dielectric and thereby not exposing copper metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.