Vertical MISFET devices
US6207977A · kind A · utility
103Cited by
10References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 21, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Oct 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
The present invention relates to processes for fabrication of Vertical MISFET devices or a stack of several of such devices. The Vertical MISFET device comprises a highly doped drain region, a non or lowly doped channel region and a source region forming a heterojunction with the channel region. The source region comprises a lowly doped part which contacts the channel region and a highly doped part which contacts the lowly doped part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.