Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same
US6207991A · kind A · utility
15Cited by
17References
19Claims
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Key dates
| Filing date | Mar 20, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Mar 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of forming non-volatile memory (e.g., an EEPROM device) and a CMOS device (e.g., a RAM), on a single die or chip, and a structure formed by the method. In one embodiment, the control gate of the storage transistor as well as the isolation gate of the isolation transistor may be formed during the same manufacturing process step, and thus may be formed of the same gate poly material and may have similar thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.