High-voltage transistor with multi-layer conduction region
US6207994A · kind A · utility
222Cited by
30References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Feb 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.