Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof
US6208004A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Aug 19, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications. Consistent with one embodiment, a process for manufacturing a polycide transistor gate electrode involves forming a cap dielectric and dielectric spacer, with the electrode exhibiting a reduced diffusion transport of dopants between an underlying doped polysilicon layer and an overlying silicide layer. The reduced transport results from the presence of a thin barrier layer between the doped polysilicon layer and silicide layer, and the gate electrode process forms a thermally-oxidized thin polysilicon side-wall film against the polysilicon layer, the barrier layer, the silicide layer, and the cap dielectric layer. The polysilicon side-wall film is used for blocking substantial oxidation of the barrier film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.