CMOS over voltage-tolerant output buffer without transmission gate
US6208178A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2000 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Feb 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An isolating output buffer is operated by a low-voltage Vcc power supply, yet can be put in a high-impedance state. The output buffer does not draw significant current when its output is driven by an external driver to a voltage above Vcc. The over-voltage on the output pad is coupled to the n-well under p-channel transistors through a fixed-gate p-channel transistor. The over-voltage from the n-well is then coupled to a source node through another p-channel transistor. The source node is the source of a p-channel transistor that drives the gate of a p-channel driver transistor driving the output pad. The source node is normally driven to Vcc by another p-channel transistor. The p-channel transistor can be split into two driver transistors that are separately driven by two isolating inverters or gates. The isolating gates have p-channel transistors connected to the source node. Using split drivers can reduce noise and di/dt when the two driver transistor are enabled at slightly different times. The output buffer is implemented entirely in CMOS without using bipolar transistors. The isolating output buffer is faster because it does not use a transmission gate in the speed path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.