Pulse amplifier with low duty cycle errors
US6208199A · kind A · utility
23Cited by
4References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 17, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Mar 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power pulse amplifier with low duty cycle errors. The amplifier provides several differential amplifier stages with a biasing and canceling network. To minimize duty cycle errors for large input signals, cascode transistors are added between the drains of the differential amplifiers and the outputs. The result is an amplifier having a duty cycle error of less than 5% at amplitude input ranges from 5 millivolts to the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.