Content addressable memory cell providing simultaneous read and compare capability
US6208544A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Sep 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The need to employ three separate cycles for write, read and compare operations for operation of a content addressable memory cell is obviated by a memory cell architecture that allows simultaneous read and compare operations, thereby reducing memory cycle time by one-third of that of a conventional CAM. To enable the data bit stored in the memory cell to be compared with a reference bit, the memory cell is coupled with a comparator, that receives inputs from the data nodes of the memory cell and a set of comparison bit input lines. Rather than supplying reference data by way of the data lines through which data is written into and read from the memory cell, as in a conventional CAM, the compare bit and its complement are coupled to the match logic exclusively of the memory cell. Since application of the comparison bit does not involve the use of the normal data read and write lines, accessing data read and write paths for the memory cell is not required. As a consequence, a read cycle and a comparison cycle may be performed simultaneously, without one affecting the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.