Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb
US6208559A · kind A · utility
24Cited by
12References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Nov 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.