Co-processor for performing modular multiplication
US6209016A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jun 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/723
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A co-processor (FIG. 2) for performing modular multiplication comprising: means for receiving B and N binary data streams (bstr, nstr); means for receiving a data value A; adder means (Add1, Add2), subtractor means (Sub1, Sub2, Sub3) and multiplier means (Mul1, Mul2) coupled to sequentially process the B and N binary data streams and the data value A to produce a modulo-reduced multiplication value (A*B) mod N; and further including exponentiation means (FIG. 6) comprising: random access memory (E-RAM) for holding an exponent value; parallel-serial interface means for receiving in parallel from the random access memory the exponent value and for producing therefrom a binary data stream E; control means (CONTROL) for receiving the binary data stream E and for initiating a squaring or a multiply operation in dependence on the value of each bit thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.