Data processing system and method for inputting data from storage devices where the data buss width for input depends on the number of memory devices
US6209049A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Nov 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system and a method for inputting data from storage devices provided in the data processing system, in which the ROM address areas in a memory map include an area for reading in a 32-bit bus mode and an area for reading in a 16-bit mode, which areas are set so that a portion of the addresses are equal. When a 32-bit data read is performed for the area used to read in 32-bit bus mode and the high-order 16 bits are invalid, it is determined that only one ROM device is mounted in the system. Therefore, accesses are performed with the area used to read in 16-bit bus mode. After determining the number of ROM devices in this way, the result is written to a mode register. The selector reads this result stored in the mode register and, when only one ROM device is mounted in the system, supplies Address A1 to the highest-order address terminal RA17 of the ROM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.