Reliable interrupt reception over buffered bus
US6209054A · kind A · utility
5Cited by
25References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reliable interrupt reception over a buffered bus utilizes a non-delayed non-posted write transaction to write data over the bus from a peripheral device to host memory. Because there is no buffering delay in a non-delayed non-posted write transaction, at the completion of the write cycle the peripheral knows that the write transaction is complete and then sends an interrupt request to the host processor requesting the host processor to service the interrupt and process the contents of the host memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.