System and method for interlocking barrier operations in load and store queues
US6209073A · kind A · utility
10Cited by
7References
21Claims
0Family size
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Inventors
Key dates
| Filing date | Apr 27, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Apr 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Storage access blocking instructions, such as the EIEIO instruction implemented within the PowerPC architecture, block other storage access instructions at the bus interface stage as opposed to the execute stage. Therefore, cacheable instructions, and other similar instructions, are allowed to complete without being blocked by such an EIEIO instruction not ordered by the EIEIO instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.