Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
US6209123A · kind A · utility
454Cited by
23References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1996 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Nov 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of automatically placing transistors of a folded transistor circuit for synthesizing rows of transistors in a semiconductor layout (172). First, an initial placement of transistors is generated (802). Next, a candidate move of transistors is selected (804). Then the change in cost of the placement resulting from applying the candidate move is evaluated (806). A decision is made to accept the candidate move based on the evaluation of its cost (808). If accepted, the move is performed (810) and the cost of the placement is updated (812). Finally, a decision to terminate the process is made (814).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.