Method for fabricating CMOS device
US6211064A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a CMOS device on a SOI, comprising the steps of: providing a SOI wafer having a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; forming a field oxide film in the semiconductor layer to define an active region in which a PMOS device and a NMOS device are to be formed in the semiconductor layer of the SOI wafer, wherein the field oxide film is formed by performing thermal oxidation process so as to apply a compressive stress to the semiconductor layer that the PMOS device is to be formed; and forming the PMOS device and NMOS device in the active region defined by the field oxide film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.