Method for relieving lattice mismatch stress in semiconductor devices
US6211095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1998 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Dec 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7624
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The first material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the second material by the first material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO.sub.2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.