Low inductance power package for integrated circuits
US6211462A · kind A · utility
233Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Nov 4, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention provides a low inductance semiconductor package for RF circuits having a flat leadframe with internal leads formed upward to be in very close proximity to the die mount pad. The die mount pad is exposed through the package backside and serves both as a ground plane and as a heat spreader. The external leads are flat and extend beyond the package edge so that good solder connections to a printed wiring board can be made and inspected. The lead tips exposed beyond the package further provide a position for mold clamping and for test probing the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.