Efficient error correction in pipelined analog-to-digital converters
US6211806A · kind A · utility
13Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 8, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Sep 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method and apparatus for correcting errors in N digital word generated by N+1 pipelined analog-to-digital converters. The method comprises the steps of: (1) synchronizing the N digital words by N groups of pipeline registers; and (2) correcting the synchronized N digital words by performing either an incrementing operation or a decrementing operation based on an adjustment value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.