Symbol-quality evaluation in a digital communications receiver
US6212246A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 1998 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | May 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a digital communications receiver, a system and method for evaluating the quality of received symbols and for initializing and adjusting a symbol clock. The invention presents a symbol quality detector that evaluates symbols which have been received by the receiver and detected in a matched filter. The received symbols are members of a constellation with elements that have purely I or purely Q components. The symbol-quality detector comprises inputs that receive the I and Q components of the symbols, and a logic block that generates the symbol-quality signal by constructing the quantity .vertline..vertline.I.vertline.-.vertline.Q.vertline..vertline.. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The present invention further comprises a digital communications receiver that uses a symbol-quality detector to evaluate its symbol clock. Still further, the present invention contemplates a method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.