Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like
US6212597A · kind A · utility
43Cited by
3References
38Claims
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Key dates
| Filing date | Jul 28, 1997 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Jul 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.