Legacy MIL-STD-1750A software emulator address translation using power PC memory management hardware
US6212614A · kind A · utility
6Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for implementing the paging and protection attributes, such as block protection and access lock and key functions promulgated in MIL-STD-1750A. The present invention takes advantage of the PowerPC microprocessor architecture to implement the paging and protection attributes required by MIL-STD-1750A in hardware. Since the paging and the protection attributes are implemented in hardware, the system performance is greatly improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.