Method and apparatus for automatic L2 cache ECC configuration in a computer system
US6212631A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Jan 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is disclosed which includes at least one microprocessor having an L2 cache, at least one memory, and basic input output system (BIOS) firmware. The L2 cache includes error checking and correcting capability (ECC). The at least one memory includes either all ECC capable memory or any combination of ECC capable and non-ECC capable memory. Lastly, the basic input output system (BIOS) firmware includes an L2 cache support feature. The L2 cache support feature includes three user-selectable options, the three options including i) L2 cache ECC ON, ii) L2 cache ECC OFF, and iii) L2 cache AUTO. Selection of L2 cache ECC ON is for enabling L2 cache ECC. Selection of L2 cache ECC OFF is for not enabling L2 cache ECC. Lastly, selection of L2 cache ECC AUTO is for automatically enabling or not enabling L2 cache ECC in response to a detection of the presence of a) all ECC capable memory or b) any combination of ECC and non-ECC capable memory, respectively. Accordingly, an optimal reliability or an optimal performance can be automatically assured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.