IDDQ test solution for large asics
US6212655A · kind A · utility
3Cited by
3References
7Claims
0Family size
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Key dates
| Filing date | Nov 20, 1997 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Nov 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3008
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method identifies Iddq test vectors to be used in IDDQ testing of large CMOS circuits. This is achieved through intelligent preprocessing techniques. By monitoring only those nodes in the circuit that may be responsible for leakage current in the steady state, the size of the simulation results file is drastically reduced. The reduced simulation results file makes simulation a viable solution for IDDQ vector identification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.