Integrated circuit test coverage evaluation and adjustment mechanism and method
US6212667A · kind A · utility
49Cited by
14References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1998 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Jul 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31835
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Testcases are run to test the design of an integrated circuit. The coverage of the testcases is evaluated and compared against one or more microarchitecture models that define the behavior of a portion of the integrated circuit. If the coverage of the testcases is not adequate, new testcases are generated to test the previously untested behavior specified in the microarchitecture models.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.