Gain matrix for hierarchical circuit partitioning
US6212668A · kind A · utility
14Cited by
33References
27Claims
0Family size
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Key dates
| Filing date | May 27, 1997 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | May 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for partitioning a group of cells in a network into a set of disjoint blocks of cells. The network is represented by a hierarchical graph with each level representing a hierarchy of resources, leaf nodes representing the blocks of cells, and edges representing interconnections between resources. A gain matrix is formed by combining a gain vector for each level of hierarchy for each possible move. Cells are moved between leaf nodes based on the gain matrix computed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.