Electrically programmable non-volatile memory cell configuration
US6215140A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Sep 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/10
Abstract
A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.