Semiconductor integrated circuit device
US6215159A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Mar 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/242
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
CMOS logic circuit CM is of a structure in which the threshold value of constituent transistors MP1, MN1, etc. thereof is set to value lower than ordinary value, and the threshold value of a stand-by state current control P-channel MOS transistor MP2 is set to value higher than the threshold value of the transistors MP1, MN1, etc. constituting the CMOS logic circuit CM. A level conversion circuit 10 outputs a signal in which low level indicates negative voltage and high level indicates the same potential VDD as that of the first power supply line P1 in dependency upon high level and low level of signal applied to control input terminal SIG to thereby carry out ON/OFF control of the P-channel MOS transistor MP2. Accordingly, lower voltage of 0V or less, or higher voltage of VDD or more is applied to the gate of the stand-by state current control MOS transistor in the CMOS logic circuit, whereby even if the power supply voltage VDD is caused to be low voltage, ON/OFF operation of the stand-by state current control MOS transistor is securely carried out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.