Dual leadframe package
US6215176A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | May 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual leadframe package. A chip including a first surface and a second surface is provided. A gate and a first source/drain region are located on the first surface, and a second source/drain region is located on the second surface. A first lead including a first innerlead and a first outerlead and a second lead including a second innerlead and a second outerlead are provided. The first innerlead is coupled to the first source/drain region, and the second innerlead is coupled to the gate. A conductive plate including a top surface and a bottom surface is provided, and the top surface is coupled to the second source/drain region. A packaging material seals the chip, the first innerlead, the outerlead and a portion of the conductive plate. The bottom surface, the first outerlead and the second outerlead are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.