Fast structure dram
US6215706A · kind A · utility
5Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/103
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.