Clock-synchronized memory
US6215725A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Jul 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock-synchronized memory includes a plurality of memory cells and a plurality of mode registers in which respectively different operation modes are set, the clock-synchronized memory outputting data stored in the plurality of memory cells in one of the respectively different operation modes and in synchronization with a clock signal. The clock-synchronized memory further includes: a detection circuit for detecting a power potential applied to the clock-synchronized memory; and a mode register selection circuit for selecting one of the respectively different operation modes, the selection being made in accordance with an output signal from the detection circuit representing the power potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.