Method and apparatus for utilizing parallel memory in a serial memory system
US6215727A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus providing parallel memory circuitry, such as for example synchronous dynamic random access memory (SDRAM) support in a computer system designed to support serial memory circuitry, such as for example Rambus dynamic random access memory (RDRAM). In one embodiment, a circuit board including a memory translator having serial memory interface logic and parallel memory interface logic is plugged into a serial memory connector on a motherboard designed to utilize serial memory circuitry. The circuit board includes parallel memory circuitry coupled to the parallel memory interface logic of the memory translator. The memory controller on the motherboard accesses the parallel memory circuitry on the circuit board through the memory translator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.