Physical layer interface device
US6215816A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Mar 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A single chip dual function 10 Base-T/100 Base-X physical layer interface device (PHY) compatible with existing 5 V parts is provided. The PHY includes a media-independent interface (MII) and connects to an unshielded twisted pair cable via an isolation transformer and a single RJ45 connector. The PHY includes built-in auto-negotiation circuitry that allows for automatic selection of half/full duplex 10 Base-T and 100 Base-TX, while auto-polarity correction circuitry ensures immunity to receive pair reversal in the 10 Base-T mode of operation. The PHY includes internal PLL circuitry that uses a single 20 MHz clock or crystal, but that is suitable for either speed mode. The PHY includes low-power and power down modes. The 10 Base-T portions of the PHY include smart squelch for improved receive noise immunity. The PHY includes high jitter tolerance clock recovery circuitry and transmit jabber detection circuitry. The 10 Base-T portions of the PHY include on board transmit waveshaping. The 100 Base-X portions of the PHY include synthesized rise time control for reduced electromagnetic interference (EMI). The PHY includes a programmable transmit voltage amplitude for 100 Base-X MLT-3 w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.