System and method for fast barrier synchronization
US6216174A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Sep 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improved method and apparatus for facilitating fast barrier synchronization in a parallel-processing system. A single input signal and a single output signal, and a single bit of state ("barrier_bit") is added to each processor to support a barrier. The input and output signal are coupled to a dedicated barrier-logic circuit that includes memory-mapped bit-vector registers to track the "participating" processors and the "joined" processors for the barrier. A "bjoin" instruction executed in a processor causes a pulse to be sent on the output signal, which in turn causes that processor's bit in the dedicated barrier-logic circuit's "joined" register to be set. When the "joined" bits for all participating processors (as indicated by the "participating" register) are all set, the "joined" register is cleared, and a pulse is sent to the input signal of all the participating processors, which in turn causes each of those processor's barrier_bit to be set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.