32-bit mode for a 64-bit ECC capable memory subsystem
US6216247A · kind A · utility
119Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 32-bit mode operation for a typical 64-bit ECC memory subsystem. In 32-bit mode, each data block will have an 8-bit ECC value, which is consistent with ECC values generated for 64-bit data. This is achieved by prefixing the data with 32 zeroes. When reading out data, memory faults can be corrected and detected using ECC techniques on a zero prefixed data block that is read out of the memory. This allows a memory subsystem to be optimized for bandwidth and latency depending upon this application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.