Thin film transistor with a multi-metal structure and a method of manufacturing the same
US6218221A · kind A · utility
83Cited by
1References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 27, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | May 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
The present invention includes forming a gate on a transparent substrate. A gate isolation layer is then formed on the gate. An amorphous silicon (a-Si) layer and n+ doped silicon layer are successively formed on the gate isolation layer. Then, the a-Si layer and the n+ doped silicon layer are patterned. A first, a second and a third metal layers are successively formed on the n+ doped silicon layer, thereby forming a multi-metal layer structure. Subsequently, a wet and a dry etching is utilized to etch the multi-metal layer, thereby defining the S/D electrodes. A passivation layer is deposited on the S/D structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.