Method of forming an alignment key on a semiconductor wafer
US6218263A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | May 7, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.