Silicide encapsulation of polysilicon gate and interconnect
US6218276A · kind A · utility
21Cited by
25References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of forming a silicide layer on the top and sidewall surfaces of a polysilicon gate/interconnect in a MOS transistor and on the exposed surfaces of the source and drain regions of the transistor. Devices produced according to the present invention may have different types of silicide formed on their gate and their source/drain electrodes. The invention achieves the advantages of silicide encapsulation of a polysilicon gate in an MOS transistor while also providing silicidation of the source/drain regions of the transistor, thereby reducing electrode resistivity in the transistor and interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.