CMOS voltage reference with post-assembly curvature trim
US6218822A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S323/907
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An apparatus and method for performing curvature trim in a voltage reference circuit that allows a curvature error to be trimmed after the circuit has been packaged. The curvature trim may be performed by switching in segments of one or more non-linear resistors, such as n-type lightly doped drain (LDD) diffused resistors, having a curvature characteristic that is opposite to the normal band-gap curvature. Specifically, a network of non-linear resistors may be selected via selection bits stored in a non-volatile memory. Since various combinations of the resistors may be selected by programming the memory, the curvature of a band-gap reference can be adjusted after final packaging. This curvature correction method achieves a reliable and accurate correction for the curvature variations associated with various process changes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.