Semiconductor memory device
US6219271A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2000 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Jan 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device enabling a reduction in size of a memory cell and higher integration. A drive transistor and a word transistor are formed in a p-type active region. Similarly, another drive transistor and another word transistor are formed in another p-type active region. A word line is wired so as to be substantially orthogonal to both of the p-type active regions. A pMOS load transistor is formed in an n-type active region, and another load transistor is formed in another n-type active region. A channel width of the drive transistor is greater than a channel width of the load transistor. Thereby, a cell area can be reduced while achieving the cell current and the SNM equivalent to those of a conventional SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.