Pulse position modulation based transceiver architecture with fast acquisition slot-locked-loop
US6219380A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Jan 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4902
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A transceiver has a pulse position modulation (PPM) encoder, automatic gain control (AGC) circuit and timing recovery circuit. The PPM encoder illustratively has a frequency divider, slot selector, and mixer. The frequency divider divides the frequency of a clock signal to which the data of the non-return to zero (NRZ) signal are aligned to produce a half frequency clock signal. The slot selector selects pulses of the clock signal and the half frequency clock signal depending on logic values of the NRZ signal and a control signal to produce first and second slot selected signals. The mixer mixes the first and second slot selected signals to produce a PPM signal of the NRZ signal. The AGC circuit illustratively has a variable gain amplifier, a hysteresis comparator, an event detector, a timer, and a counter. The variable gain amplifier amplifies the PPM signal using a dynamically adjusted gain that depends on an inputted digital control value. The counter increments the inputted digital control value according to a clock signal outputted from the timer to increase the gain. The hysteresis comparator detects a signal level of the amplified PPM signal. The event detector causes the co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.