Jitter resistant clock regenerator
US6219396A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | May 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/242
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A jitter resistant clock regenerator for receiving program data transmitted on a transmission channel in synchronism with a transmission clock signal and cancelling jitter, having occurred on the channel, to restore from the transmitted program data a highly accurate program clock signal from which the jitter is removed. The regenerator includes a buffer for temporarily storing transmitted data received over the channel. A read clock selector monitors the buffer to determine the amount of the transmitted data stored in the buffer, and selects one of read clock signals in response to the data amount. A program clock acquisition circuit reads out the transmitted data from the buffer in response to a read clock signal selected by the selector, and restores the clock signal of the program data from the transmitted data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.