Optimized rounding in underflow handlers
US6219684A · kind A · utility
9Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Sep 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49915
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding mode to generate an underflowed operand. The underflowed operand is denormalized and providing characteristic bits. A rounding bit is generated based on the characteristic bits. The rounding bit is merged with the denormalized operand to generate the rounded result operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.