Methods and apparatus for variable length SDRAM transfers
US6219747A · kind A · utility
Inventors
Key dates
| Filing date | Jan 6, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Jan 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.