Massively parallel computer including auxiliary vector processor
US6219775A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Mar 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing inst…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.