Dithering logic for the display of video information
US6219838A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Aug 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N11/042
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Dithering logic includes a number of programmable linear feedback shift registers (LFSRs), each configured to receive one of a number of color components (e.g., red-green-blue) of a video information signal as an input and to provide one of a number of dithered color components of the video information signal as an output. The dithered color components each include a greater number of bits than the color components. The LFSRs may be configured so that each LFSR includes a mask register configured to accept a characteristic polynomial. The dithering logic may be included in a set-top controller of a computer network that is organized to include a graphics processor communicatively coupled to the set-top controller. The dithering logic is thus configured to introduce pseudorandom noise into video information signals transmitted from the graphics processor to the set-top controller in accordance with one or more characteristic polynomials. Preferably, the characteristic polynomials are primitive polynomials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.