Synchronous calibration test circuit for use in recording systems
US6222375A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | May 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A synchronous calibration test circuit in accordance with the principles of this invention that uses a bandgap reference voltage of a PRML chip and a write clock synthesizer to generate an output reference calibration signal comprising a programmable frequency and whose amplitude is invariant with environmental conditions. This reference signal is injected at the input of a signal path of the PRML chip and measured after the PRML's A/D converter using the synchronous test calibration circuit of this invention. Since the programmable frequency reference signal is insensitive to voltage supply fluctuations as well as temperature and process variations this reference signal can be used to measure and characterize changes in the transfer function of the analog signal path of the PRML chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.