Variable analog delay line for analog signal processing on a single integrated circuit chip
US6222409A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Jul 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Programmable analog delay line devices for analog signal processing are constructed on a single integrated circuit chip using a switched capacitor storage scheme for short-term storage of the voltage or charge waveform. These devices provide variable maximum delay times without signal attenuation and with delay-to-risetime ratios of up to 10.sup.2 to 10.sup.3. A vector array of switched capacitor analog storage elements may be arranged in a ring-buffer topology, with the number of switched capacitor elements ranging from between about 10 and about 10.sup.5. Two internal counters incremented by a common clock keep track of the variable delay between an input signal and an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.